An Expert System for VLSI Layout

This thesis addresses the problem of automatic layout generation for the random logic modules in a VLSI chip. We propose a new top-down methodology that eliminates the weakness of a standard cell layout system. Our methodology decomposes the module layout problem into a smaller leaf-cell layout problem and designs the leaf-cells exactly according to their environmental needs.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Lin, Youn-Long Steve

• Computer Science

Identifier

(UMI)AAI8803119

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69584