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University of Illinois at Urbana-Champaign

Floor Planning and Global Routing in an Automated Chip Design System

Abstract

dc:description

In this thesis, a systematic approach has been taken to generating either a slicing or non-slicing structure floorplan. For non-slicing structure layout, the system is divided into initial placement, initial floorplan construction and a floorplan packing. A new analytical model is introduced for the initial placement. Unlike previous analytical methods in which modules are modeled as points, the area of each module as well as its interconnections are considered in the objective function. An energy function is defined between any two modules and the objective is to minimize the total energy. A new module packing algorithm is introduced. A novel feature of the algorithm is that modules are shifted back to obtain the maximal slack region for modules. The slack region provides useful information for reducing the critical path of the chip. For the slicing structure approach, after the initial placement, slicing and slicing structure optimization are performed. Slicing is used to obtain a slicing structure topology for the modules. It recursively bisects the initial placement result according to the area distribution. Slicing structure optimization is used to determine an optimal shape for all the modules, given the chip aspect ratio constraints. These algorithms are integrated and linked by a common database and are driven by a main program using hierarchical graphic menu entries. Experimental results show that the non-slicing structure approach achieves better area utilization and shorter wiring length than the slicing structure floorplan methodology, especially when the number of fixed-shaped modules is large.

Degree

thesis:*
Name thesis:degree_name
Ph.D.
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Computer Science
Grantor
University of Illinois at Urbana-Champaign
Year dc:date
2014

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Hsu, Yu-Chin
Contributors dc:contributor
  • Kubitz, William,

Subjects

dc:subject × 1

Identifiers

dc:identifier.*
Identifier
(UMI)AAI8803071
OAI identifier oai:identifier
oai:www.ideals.illinois.edu:2142/69580

Chain of custody

source
Harvested from
University of Illinois - Urbana-Champaign
Base URL
www.ideals.illinois.edu/oai-pmh
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Hsu, Yu-Chin. Floor Planning and Global Routing in an Automated Chip Design System. Dissertation thesis, University of Illinois at Urbana-Champaign, 2014. http://hdl.handle.net/2142/69580