Fault Tolerance and Performance Improvement in Multiprocessor Interconnection Networks (shuffle-Exchange, Redundant-Path Array Processors)

A general class of fault-tolerant multistage interconnection networks is introduced, wherein fault tolerance is achieved by providing non-unique paths between each input and each output. The topology of the multiple paths is specified by means of a redundancy graph. Different techniques for constructing such networks are presented and relevant properties and control algorithms investigated. Several implementation issues, including concurrent detection of errors and effective utilization of the redundant paths, are discussed and resultant improvements in network reliability analyzed under various circumstances. Performance of the network operating in both circuit switched and packet switched modes is evaluated in detail. Redundant path networks are shown to provide significant tolerance to faults at minimal costs, as well as improvements in performance and very graceful degradation.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Padmanabhan, Krishnan

• Computer Science

Identifier

(UMI)AAI8422791

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69532