Multicomputer Interconnection Using Word Parallel Shift Register Ring Networks

This thesis surveys existing processor-memory interconnection structures and investigates the word-parallel ring network in detail. It proposes a design for constructing a multimicrocomputer using such a network. The ring network operates as both a memory switch interconnecting processor nodes and shared memory, and as a high speed block transfer medium between nodes. The major limitation of the approach is the loop transit delay, which grows in direct proportion to ring size. Provided the loop time is small enough compared to the memory cycle time the operation will be acceptable. The ring network is attractive when ring clock times are much faster than memory cycle time.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Horton, Kurt Harold

• Computer Science

Identifier

(UMI)AAI8422083

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69530