Layout Synthesis of Nmos Gate-Cells

The NMOS Gate-Cell, a regular structure that supports gate level implementations of random logic is introduced. It is an extension of the Weinberger array, where allowing input/output terminals on all four edges resulted in an improved interconnect flexibility. Intercell routing is allowed to traverse the cells such that interconnection by abutment is achieved. The cells are implemented with AND-OR-INVERT static NMOS gates, and are based on multigrid cell models which permit controlled area changes when device sizes are adjusted to accomodate modified propagation-delay requirements.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Luhukay, Joseph F.P.

• Computer Science

Identifier

(UMI)AAI8324598

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69517