Compilation of Register Transfer Language Descriptions Into Silicon

This thesis describes a design automation system for compiling high-level-language behavioral descriptions of VLSI systems into layout descriptions. The optimization goal is to generate the minimum-area layout that meets given time specifications and technological constraints. This goal is achieved by basing the system on an innovative design methodology, the most important features of which are structured design (hierarchy and regularity), intracell wiring strategy, algorithmically defined cells, and efficient handling of Register Transfer (RT) operators which are represented by Boolean recurrences.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Bilgory, Avinoam

• Computer Science

Identifier

(UMI)AAI8302807

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69509