Back to results
University of Illinois at Urbana-Champaign
The Design of Programmable Logic Arrays With Concurrent Error Detection
Abstract
dc:descriptionThis research has mainly centered on the design of PLAs with concurrent error detection. The PLAs are designed to achieve the totally self-checking (TSC) goal of producing a noncode word as the first erroneous output due to a fault. Since a strongly fault secure (SFS) circuits have been shown to be the largest class of circuits that achieve the TSC goal, we concentrate on the design of SFS PLAs rather than TSC PLAs. The concept of SFS circuits is discussed and the relationship between TSC and SFS circuits is explored. The fault assumptions for SFS circuits and the necessary conditions for a circuit to be SFS under these fault assumptions are presented.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Computer Science
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2014
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Mak, Gong-Po Philip
Subjects
dc:subject × 1Identifiers
dc:identifier.*- Identifier
- (UMI)AAI8218516
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/69507