Modeling and Simulation of High-Speed Digital Circuit Interconnections

The advent of fast devices and the demand for smaller integrated circuits and packages have led to a high density of components and closely packed interconnects in both on-chip and off-chip levels. Size and spacing of interconnects have been dramatically reduced in recent years which have led to various electrical phenomena involving waveform distortion attenuation, and crosstalk causing a higher level of noise and possibly data error in fast computer or telecommunication networks.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Schutt-Aine, Jose Emmanuel

Contributors dc:contributor

• Mittra, Raj

• Engineering, Electronics and Electrical

Identifier

(UMI)AAI8823244

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69403