Reducing Interprocessor Communication in Parallel Architectures: System Configuration and Task Assignment

Most future supercomputers will be based on parallel processing architectures. Currently, many applications with sufficient parallelism cannot efficiently run on large parallel processing systems because interprocessor communication and synchronization significantly degrade performance. Interprocessor communication is incurred on message passing systems when two processors exchange data through communication links and in shared memory systems when variables stored in shared memory are written into by one processor and then read out by another processor.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Abraham, Santosh George

Contributors dc:contributor

• Davidson, Edward S.

• Engineering, Electronics and Electrical

Identifier

(UMI)AAI8823067

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69392