Testing and Fault-Tolerance Aspects of High-Density VLSI Memory

Presented in this thesis is a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for RAMs and CAMs are developed for a broad class of parametric and pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for the testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed-up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency of the proposed algorithms is by a factor of $O(\sqrt{n})$. Concepts of planar tessellation and graph theory have been employed to design optimal test algorithms. In embedded applications, where neither the address and read/write lines are externally controllable nor are the output lines directly observable, the proposed algorithms have been adapted for Built-In Self-Test (BIST) implementation. It is also shown that the proposed design for testability is amenable to random testing in the event BIST hardware cannot be integrated at the site of the memory. Markov chain analysis has been made to estimate the detection quality and fault coverage for test length of different sizes.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Mazumder, Pinaki

• Engineering, Electronics and Electrical

Identifier

(UMI)AAI8815386

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69386