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University of Illinois at Urbana-Champaign
Topics in Totally Self-Checking Circuits and Testable Cmos Circuits
Abstract
dc:descriptionA Totally Self-Checking (TSC) circuit belongs to a class of circuits used for Concurrent Error Detection (CED) purposes. It consists of a functional circuit that has encoded inputs and outputs and a checker that monitors these outputs and gives an error indication. It is known that the traditional stuck-at fault model is not sufficient to model realistic physical failures. Techniques for implementing existing gate-level TSC circuits in nMOS, Domino-CMOS and standard CMOS technologies, so that they are TSC with respect to physical failures, are described. Design methods that reduce the transistor count, delay and the number of tests of TSC checkers are also given.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2014
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Jha, Niraj Kumar
Subjects
dc:subject × 1Identifiers
dc:identifier.*- Identifier
- (UMI)AAI8600221
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/69324