Switch-Level Timing Simulation of Mos Vlsi Circuits

This dissertation deals with the development of a fast and accurate simulation tool for very-large-scale integrated (VLSI) circuits of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented in this thesis can handle only n-channel MOS (NMOS) circuits, but are easily extendible to handle complementary MOS (CMOS) circuits as well.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2014

Author dc:creator

• Rao, Vasant Bangalore

• Engineering, Electronics and Electrical

Identifier

(UMI)AAI8521866

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/69310