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University of Illinois at Urbana-Champaign
A Theory for Algorithm-Based Fault Tolerance in Array Processor Systems
Abstract
dc:descriptionThe concept of algorithm-based fault-tolerance deals with system-level methods for obtaining reliable results from computations, especially when performed on array processor systems. In this scheme, algorithms have their outputs encoded in a system-level error-detecting or -correcting code. The algorithms rearrange the computations to allow an array processor system with a faulty processor to produce either a noncodeword output or the correct output. The algorithms also provide appropriate error-checking procedures which operate on the high-level encoded data.
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2014
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Banerjee, Prithviraj
Subjects
dc:subject × 1Identifiers
dc:identifier.*- Identifier
- (UMI)AAI8521714
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/69305