Single-layer bus routing for high-speed boards

As the clock frequencies used in industry increase, the timing requirements on high-speed boards become very tight. Since wire length is directly proportional to wire delay of the buses that connect each chip on high-speed boards, each wire in the bus has to be tightly bounded by the maximum and minimum lengths during routing. These rigid requirements cause challenges for automatic routing. Therefore, more aggressive routing algorithms are required for current industrial circuits. This thesis intends to improve Ozdal and Wong's previous work, which is an algorithmic study of single-layer bus routing on high-speed boards. Their routing algorithm assumes that there are no boundaries in the grid during routing, and the maximum-length bound for each net is always met. This thesis modifies their code so that it does not make those assumptions. As a result, the program can now handle boundaries with wire snaking to meet the minimum-length bound and use diagonal wires if the Manhattan distance between the two terminal pins cannot satisfy the maximum-length bound.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2012

Author dc:creator

• Chang, Yun Wei

Contributors dc:contributor

• Wong, Martin D.F.

• Single Layer Bus
• High-Speed Printed Circuit Board

Statement dc:rights

• Copyright 2011 Yun Wei Chang

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/29764

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/29764