An evaluation framework for massively parallel accelerator processors

In this thesis, I describe the evaluation framework for Rigel, a 1024-core single-chip accelerator architecture designed for high throughput on visual computing and scientific workloads. I present an integrated evaluation framework for investigating co-designed architecture, compilers, programming models, and RTL implementation for massively parallel chip multiprocessors (CMPs). The research objective of the Rigel project, designing a prototype thousand-core chip, led to the development of the framework presented in this thesis. I describe the tools and techniques which enabled this work. The goal of this thesis is not to evaluate specific design tradeoffs, but to describe the tools we have developed for making these decisions. I motivate and describe our integrated performance simulator, code generator, and RTL implementation for evaluation of a novel 1024-core accelerator architecture. I demonstrate the utility of a flexible hardware-software interface supporting an evolving ISA for architectural design space exploration. Although I present experiences related to a particular design, the methods applied and lessons learned are more broadly applicable. I summarize some of the published work which this framework has enabled.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Johnson, Daniel R.

Contributors dc:contributor

• Patel, Sanjay J.

• Accelerator
• Chip Mulitprocessor
• Parallel Processing

Statement dc:rights

• Copyright 2011 Daniel R. Johnson

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/24396

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/24396