FPGA-based digital phase-locked loop analysis and implementation

The thesis presents a digital PLL project that will be used as an ECE 463 lab module and serve as a platform for future communication research projects. Field Programmable Gate Array (FPGA) technology is used for all digital signal processing tasks. A Direct Digital Synthesizer (DDS) is used to synthesize analog output, the frequency of which is controlled digitally by the FPGA. This system is implemented in a way that makes it educational and suitable for a lab module. Unlike purely digital PLL, this project involves several analog circuits soldered on PCBs, which will help the students visualize the signal flow in the PLL and get some exposure to mixed-signal systems.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Hu, Dan

Contributors dc:contributor

• Schmitz, Christopher D.
• Franke, Steven J.

• digital Phase-locked loop (PLL)
• Field Programmable Gate Array (FPGA)-based implementation
• Direct Digital Synthesizer (DDS)

Statement dc:rights

• Copyright 2011 Dan Hu

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/24165

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/24165