Exploiting multiprocessor memory hierarchies for operating systems

With the increasing gap between processor speed and memory speed, a sophisticated memory hierarchy is key to high performance. However, the operating system tends to use the memory hierarchy poorly. This thesis presents a comprehensive characterization and optimization of the performance of multiprocessor memory hierarchies for operating systems. The operating system instruction cache misses are reduced by 81% using a code reorganization scheme tailored to the operating system, guarded sequential prefetching, and stream buffers. The operating system data cache misses are reduced by 53% using a DMA-like pipelined block transfer engine, a selective update protocol, data relocation and privatization, and data prefetching in miss hot spots. The overall OS time is reduced by 32%. The cost-performance trade-offs of the software/hardware optimization schemes are also discussed.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Xia, Chun

Contributors dc:contributor

• Torrellas, Josep

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1996 Xia, Chun

Language dc:language

eng

Identifier

9780591089219
AAI9702719
(UMI)AAI9702719

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/23801