Interconnection networks and data prefetching for large-scale multiprocessors: Design and performance

Increasing computing power demands higher memory performance than ever before, and memory access becomes a more serious bottleneck in high-performance computer systems. Therefore, reducing memory access latency or hiding the latency is crucial to achieving high performance. In shared memory multiprocessor systems, where memory access must traverse interconnection networks, the system performance and costs are directly affected by interconnection networks. Latency hiding techniques such as data prefetching affect interconnection network and memory performance by demanding more bandwidth. This dissertation studies interconnection networks and data prefetching.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Kim, Sun-il

Contributors dc:contributor

• Veidenbaum, Alexander V.

• Computer Science

Statement dc:rights

• Copyright 1995 Kim, Sunil

Language dc:language

eng

Identifier

AAI9624392
(UMI)AAI9624392

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/23746