Timing-driven optimization problems in VLSI CAD

We study several optimization problems that arise in the design of VLSI circuits, with the satisfaction of timing constraints as the primary objective. We focus on problems where the underlying architecture is regular. Field Programmable Gate Arrays (FPGAs), identical standard cell based architectures and WSI arrays of blocks having a regular structure are the major architectures that are regular. The regularity of these architectures allows us to use powerful graph theoretic techniques that would not be possible otherwise.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Mathur, Anmol

Contributors dc:contributor

• Liu, C.L.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1995 Mathur, Anmol

Language dc:language

eng

Identifier

AAI9624430
(UMI)AAI9624430

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/23386