Parallel algorithms for test generation and fault simulation

With increase in complexity of digital circuits, it has become extremely important to detect faults to ensure correct operation of a digital circuit. Since test generation and fault simulation for circuits of VLSI complexity can take a prohibitive amount of time, speeding up test generation and fault simulation algorithms by either using better uniprocessor heuristics or by using the tremendous computing power available on multiprocessors thus becomes important. The design and analysis of parallel algorithms for test generation and fault simulation are the focus of this thesis research.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Patil, Srinivas

Contributors dc:contributor

• Banerjee, Prithviraj

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1991 Patil, Srinivas

Language dc:language

eng

Identifier

AAI9124467
(UMI)AAI9124467

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22981