Parallel algorithms for placement and routing in VLSI design

The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Past research has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. In this thesis, we propose two new parallel algorithms for two VLSl synthesis tasks, standard cell placement and global routing.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Brouwer, Randall Jay

Contributors dc:contributor

• Banerjee, Prithviraj

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1991 Brouwer, Randall Jay

Language dc:language

eng

Identifier

AAI9136553
(UMI)AAI9136553

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22819