Parallel algorithms for logic synthesis

De, Kaushik

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University of Illinois at Urbana-Champaign

Parallel algorithms for logic synthesis

dc:creator De, Kaushik

thesis:degree_name Ph.D.

dc:date2011

Abstract

dc:description

U of I Only

Degree

thesis:*

Name thesis:degree_name: Ph.D.
Level thesis:degree_level: Dissertation
Discipline thesis:degree_discipline: Electrical and Computer Engineering
Grantor: University of Illinois at Urbana-Champaign
Year dc:date: 2011

Author and committee

dc:creator, dc:contributor.*

Author dc:creator: De, Kaushik
Contributors dc:contributor: Banerjee, Prithviraj

Subjects

dc:subject × 2

Rights

dc:rights

Language dc:language: eng

Identifiers

dc:identifier.*

Identifier: AAI9411602
(UMI)AAI9411602
OAI identifier oai:identifier: oai:www.ideals.illinois.edu:2142/22732

Chain of custody

source

Harvested from: University of Illinois - Urbana-Champaign
Base URL: www.ideals.illinois.edu/oai-pmh
Last updated: 2026-07-22
Source record: OAI-PMH GetRecord

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citation

De, Kaushik. Parallel algorithms for logic synthesis. Dissertation thesis, University of Illinois at Urbana-Champaign, 2011. http://hdl.handle.net/2142/22732

Parallel algorithms for logic synthesis

Abstract

Degree

Author and committee

Subjects

Rights

Identifiers

Chain of custody

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