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University of Illinois at Urbana-Champaign
Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
Abstract
dc:descriptionIn this thesis, we address timing-constrained placement and routing in symmetrical field-programmable gate arrays (FPGAs).
Degree
thesis:*- Name thesis:degree_name
- Ph.D.
- Level thesis:degree_level
- Dissertation
- Discipline thesis:degree_discipline
- Electrical and Computer Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2011
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Raman, Srilata
- Contributors dc:contributor
-
- Liu, C.L.
Subjects
dc:subject × 2Rights
dc:rights- Statement dc:rights
-
- Copyright 1994 Raman, Srilata
- Language dc:language
- eng
Identifiers
dc:identifier.*- Identifier
-
AAI9512518
(UMI)AAI9512518 - OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/22655