Logic synthesis and optimization algorithms

As VLSI integration size and chip complexity keep increasing, logic design is becoming more complex and it must be automated. The increasing demand for ASIC (Application Specific Integrated Circuits) also needs design efficiency and cost effectiveness which can only be achieved by effective automatic logic synthesis tools. In this thesis, two important network realization means, PLA's and multi-level networks (i.e., random logic networks), are studied, and effective algorithms are developed for the use as automatic logic synthesis tools.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Year dc:date

2011

Author dc:creator

• Chen, Kuang-Chien

Contributors dc:contributor

• Muroga, Saburo

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1991 Chen, Kuang-Chien

Language dc:language

eng

Identifier

AAI9124394
(UMI)AAI9124394

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22282