Techniques for sequential circuit automatic test generation

Test pattern generation has progressed to a stage at which automatic test generation gives satisfactory fault coverage on almost any combinational circuit. However, the same is not true of sequential circuit test generation. While scan-based approaches can convert the sequential circuit into a combinational circuit for testing purposes, the cost of a complete scan design methodology can be prohibitive in both area overhead and performance degradation. Therefore, an efficient sequential circuit test generation system which generates tests for all detectable faults and identifies all untestable faults in the original design is necessary. The information on untestable faults could be used to add minimal design for test hardware to make these faults testable.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Niermann, Thomas Michael

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1991 Niermann, Thomas Michael

Language dc:language

eng

Identifier

AAI9136684
(UMI)AAI9136684

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/22192