The analysis and synthesis of efficient algorithm-based error detection schemes for hypercube multiprocessors

Numerous algorithms for computationally intensive tasks that are suitable for execution on hypercube multiprocessors have been developed by researchers. In this thesis, we look at parallel algorithm design from a different perspective: the provision of on-line detection of hardware errors using software techniques without any hardware modifications. This approach is called Algorithm-based error detection. We report on the implementation of system-level error detection mechanisms for four parallel applications on a 16-processor Intel iPSC-2/D4/MX hypercube multiprocessor: (1) matrix multiplication; (2) Fast Fourier Transform; (3) QR factorization; (4) singular value decomposition. We describe extensive studies of the error coverage of our system-level error detection schemes in the presence of finite precision arithmetic which affects our system-level encodings.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Balasubramanian, Vijay

Contributors dc:contributor

• Banerjee, Prithviraj

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1991 Balasubramanian, Vijay

Language dc:language

eng

Identifier

AAI9136536
(UMI)AAI9136536

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21773