Techniques to speedup test generation for VLSI circuits

The increasing complexity of logic circuits has made the problem of test generation intractable. In this dissertation we investigate three different techniques to speed up the test generation process. The first approach attempts to exploit the hierarchy inherent in any complex digital design. An intermediate high-level representation is proposed, and algorithms to perform forward implication and backtracing in the proposed framework are developed. Results of test generation experiments based on this approach are also presented.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Chandra, Susheel Jagdish

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1989 Chandra, Susheel Jagdish

Language dc:language

eng

Identifier

AAI9010821
(UMI)AAI9010821

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21314