Compiler-directed cache coherence strategies for large-scale shared-memory multiprocessor systems

The cache coherence maintenance problem has been the major obstacle in using private cache memory to reduce memory access latency in large-scale multiprocessor systems. Two compiler-directed solutions, the fast selective invalidation scheme and the version control scheme, are proposed in this work. Contrary to the existing hardware-based approach, the proposed schemes expose caches to software-directed management techniques which have the advantage of requiring no global communication and maintaining expandability of the multiprocessor systems. The fast selective scheme employs compile-time flow analysis techniques to detect cache data that contain obsolete values, and uses simple hardware to prevent using such data. The version control scheme defines the concept of version of a program variable to maintain up-to-date copies in the cache and solves the difficult problem of preserving temporal locality in parallel execution. Unlike existing software-directed schemes, both schemes achieve selective invalidation with very low time penalty. The version control scheme is also extended to hierarchical cache systems for which no satisfactory solutions exist. Detailed discussion on the development of these schemes and their proofs are presented. Finally, experimental data by simulation are shown to support the advantage of the schemes.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Cheong, Hoichi

Contributors dc:contributor

• Patel, Janak H.

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1990 Cheong, Hoichi

Language dc:language

eng

Identifier

AAI9021663
(UMI)AAI9021663

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/21265