Algorithmic results on physical design problems in VLSI and FPGA

Various physical design problems in Very Large Scale Integrated (VLSI) circuits and Field-Programmable Gate Arrays (FPGA) are studied in this thesis. Specifically, we study (1) the area minimization problem in floorplans with L-shaped modules; (2) the channel routing problem in the single layer customization technology; (3) the area routing problem in the channelless single layer customization technology; (4) the design of new routing architectures and algorithms for FPGAs; (5) the congestion-balanced approach for the FPGA placement problem.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Sun, Yachyang

Contributors dc:contributor

• Liu, C.L.

• Mathematics
• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1994 Sun, Yachyang

Language dc:language

eng

Identifier

AAI9512566
(UMI)AAI9512566

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20822