Partitioning algorithms for parallel circuit simulation

Circuit simulation is an indispensable tool in the design and analysis of Very Large Scale Integrated (VLSI) circuits. The most widely used circuit simulators rely on direct methods and offer the most accurate, reliable, and technology-independent means of simulating integrated circuits. The simulation process is inherently very computation intensive and, hence, can require a significant portion of the computational resources available for the development of VLSI circuits. With the use of multiprocessor computers becoming more widespread, there exists an opportunity to speed up the simulation by partitioning the circuit so that the computation may be spread among the processors. To accomplish this, the circuit is partitioned into subcircuits using a node tearing method. If the circuit matrix is ordered subcircuit by subcircuit followed by the tearing nodes, then the matrix takes a bordered-block-diagonal form and the LU-factorization of the diagonal blocks may take place in parallel. This thesis defines the important objectives for this partitioning task and presents two algorithms that may be used to meet the partitioning goals. The first algorithm is an iterative improvement algorithm and the second is a network flow algorithm. Partitioning results and speedups are given for a variety of circuits.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Engineering, Electronics and Electrical

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Yeh, David Ching-kai

Contributors dc:contributor

• Rao, Vasant B.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1990 Yeh, David Ching-kai

Language dc:language

eng

Identifier

AAI9026360
(UMI)AAI9026360

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20676