Performance evaluation of vector machine architectures

Vector machines are well known for their high-peak performance, but the delivered performance varies greatly over different workloads and depends strongly on compiler optimizations. Recently it has been claimed that several horizontal superscalar architectures, e.g., VLIW and polycyclic architectures, provide a more balanced performance across a wider range of scientific workloads than do vector machines. The purpose of this research is to study the performance of register-register vector processors, such as Cray supercomputers, as a function of their architectural features, scheduling schemes, compiler optimization capabilities, and program parameters. The results of this study also provide a base for comparing vector machines with horizontal superscalar machines.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Tang, Ju-ho

Contributors dc:contributor

• Davidson, Edward S.

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1989 Tang, Ju-ho

Language dc:language

eng

Identifier

AAI8924954
(UMI)AAI8924954

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/20397