Logic optimization of MOS networks

The logic networks that can be put on a single chip continues to grow in size and complexity. There is thus an increasing need for designers to rely on the assistance of computer-aided design tools to provide a fast design turnaround and reduce design errors. Logic design (or logic synthesis) is one major step in the ASIC VLSI design cycle in which automation is playing an increasingly important role in recent years. In this thesis, we describe an algorithm, SYLON-REDUCE, that can be used in automated logic synthesis tools for the logic optimization of MOS networks.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Limqueco, Johnson Chan

Contributors dc:contributor

• Muroga, Saburo

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1992 Limqueco, Johnson Chan

Language dc:language

eng

Identifier

AAI9236519
(UMI)AAI9236519

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19825