Design, analysis and reconfiguration of defect-tolerant VLSI and parallel processor arrays

In this thesis, several design, analysis and reconfiguration problems in defect-tolerant VLSI and parallel processor arrays are studied. The NP-hard memory array reconfiguration problem is formulated as a random graph problem, and a provably average-case polynomial time algorithm is presented, while all previous memory reconfiguration algorithms were given without an average-case time complexity analysis. The implemented algorithm runs faster than existing heuristics when the problem size is large. For reconfigurable pipelines, an analytical estimation of the yield is given, while all previous yield estimations were through experiments. A large area defect-tolerant tree architecture is designed that has 99% harvest rate, while all previous designs have harvest rate that is asymptotically 0%. Finally, a general framework for computing the optimal spare allocation is developed for many VLSI redundant systems.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

1992

Author dc:creator

• Shi, Weiping

Contributors dc:contributor

• Fuchs, W. Kent

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1992 Shi, Weiping

Language dc:language

eng

Identifier

AAI9305693
(UMI)AAI9305693

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19803