Fault sensitivity and wear-out analysis of VLSI systems

This thesis describes simulation approaches to conduct fault sensitivity and wear-out failure analysis of VLSI systems. A fault-injection approach to study transient impact in VLSI systems is developed. Through simulated fault injection at the device level and subsequent fault propagation at the gate, functional and software levels, it is possible to identify critical bottlenecks in dependability. Techniques to speed up the fault simulation and to perform statistical analysis of fault impact are developed. A wear-out simulation environment is also developed to closely mimic dynamic sequences of wear-out events in a device through time, to localize weak location/aspect of target chip and to allow generation of Time-to-Failure (TTF) distribution of a VLSI chip as whole. First, an accurate simulation of a target chip and its application code is performed to acquire real workload trace data on switch activity. Then, using this switch activity information, wear-out of the each component of the chip is simulated using Monte Carlo techniques.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Choi, Gwan Seung

Contributors dc:contributor

• Iyer, Ravishankar K.

• Engineering, Aerospace
• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1994 Choi, Gwan Seung

Language dc:language

eng

Identifier

AAI9512332
(UMI)AAI9512332

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19060