Hierarchical timing-driven partitioning and placement for symmetrical FPGAs

Field-programmable gate arrays (FPGAs) allow circuit designers to perform quick prototyping and development. In this thesis we attempt to partition and place a hierarchically described system on multiple FPGA chips so as to minimize the maximum delay through the system. We exploit the given hierarchy to achieve computational speedup. Delay estimation is done using an accurate empirical model. The major contributions of this thesis include multichip partitioning, accurate routing delay estimation and hierarchical timing-driven placement to avoid timing problems in FPGAs.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Karnik, Tanay

Contributors dc:contributor

• Kang, Sung Mo

• Engineering, Electronics and Electrical
• Computer Science

Statement dc:rights

• Copyright 1995 Karnik, Tanay

Language dc:language

eng

Identifier

AAI9624381
(UMI)AAI9624381

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/18976