Hardware acceleration for sparse Fourier image reconstruction

Several supercomputer vendors now offer reconfigurable computing (RC) systems, combining general-purpose processors with field-programmable gate arrays (FPGAs). The FPGAs can be configured as custom computing architectures for the computationally intensive parts of each application. In this paper we present an RC-based hardware accelerator for an important medical imaging algorithm: iterative sparse Fourier image reconstruction. We transform the algorithm to exploit massive parallelism available in the FPGA fabric. Our design allows different ways of chaining custom pipelined vector engines, so that different computations can be carried out without reconfiguration overhead. Actual runtime performance data show that we achieve up to 10 times speedup compared to the software-only version. The design is estimated to provide even more speedup on a next-generation RC platform.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2010

Author dc:creator

• Dinh, Quang S.

Contributors dc:contributor

• Bresler, Yoram

• Hardware Acceleration
• Sparse Image Reconstruction
• Field-Programmable Gate Array (FPGA)
• Reconfigurable Computing

Statement dc:rights

• Copyright 2009 Quang Sy Dinh

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/16848

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/16848