Bus scheduling implementation on the cell processor

Real-time computing is the study of hardware and software systems that are subject to a “real-time constraint” - i.e., strict deadline guarantees. With uncontrollable cache and front side bus, in the modern computer architectures, the estimation of a tight bound, worst case execution time (WCET) is difficult. The new generation computer architecture, Cell Broadband Engine Architecture (CBEA), has a software controlled front side bus (i.e. Element Interconnect Bus) that helps moderate the unpredictable task execution time problem. The CBEA is a heterogeneous chip system containing one Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs), each having an internal independent local storage memory. In this thesis, using CBEA as a platform, I implemented an interrupt based scheduling framework that uses Element Interconnect Bus (EIB) in a temporally predictable manner. The framework is built by abstracting away low-level architectural features. Experiments were also performed to show that the real-time transactions of feasible transaction sets are executed before deadline when scheduled according to a real-time scheduling algorithm, while the same transactions can miss their deadlines when scheduled according to an arbitrary (non-real-time) scheduling policy.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2010

Author dc:creator

• Chivukula, Deepti K.

Contributors dc:contributor

• Caccamo, Marco

• Bus Scheduling
• Cell Processor

Statement dc:rights

• Copyright 2010 Deepti Kumar Chivukula

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/16224

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/16224