Electrochemical random access memory as deep learning accelerators

The ever-expanding capabilities of machine learning are powered by exponentially growing complexity of deep neural network (DNN) models, requiring more energy and chip-area efficient hardware to carry out increasingly computational expensive model-inference and training tasks. Electrochemical random-access memories (ECRAMs) are developed specifically to implement efficient analog in-memory computing for these data-intensive workloads, showing some critical advantages over competing memory technologies mostly developed originally for digital electronics. In this Ph.D. dissertation, we investigated energy efficient electronic devices based on a CMOS compatible ECRAM consisting of WO3 matrix and proton carrier. The system has capability to switch between a very large number of memristive states with a high level of symmetry, small cycle-to-cycle variability, and low energy consumption; and they simultaneously exhibit good endurance, long data retention, fast switching speed. We have designed and demonstrated a novel ECRAM architecture featuring layers of channel material, solid-state electrolyte, and a dedicated ion-storage compartment. Traditional ECRAMs often face a trade-off between switching speed and CMOS compatibility. To achieve faster switching speeds, smaller ions such as Li+ have typically been used, prioritizing speed but complicating fabrication processes. Conversely, using O2- ions enhances CMOS compatibility, though at the cost of reduced switching speeds due to the larger size of the oxygen ion. In our study, we have utilized protons to simultaneously address both issues. Our ECRAM, constructed with CMOS-compatible metal oxides, operates by shuffling protons. Moreover, with a symmetric gate stack, the device can be controlled with voltage pulses, allowing for high-speed and symmetric analog programming with minimal variability. This analog ECRAM serves as a foundational block for in-memory computing, significantly reducing energy consumption and latency in AI training and inference tasks. We also demonstrate monolithic integration of ECRAM with silicon transistors to form pseudo-crossbar arrays. These arrays are crucial as they enable the execution of matrix multiplication directly on the ECRAM array, marking a significant advancement in hardware design. The importance of pseudo-crossbar arrays extends to their capacity to facilitate both training and inference phases of deep neural networks, directly within the memory. This integration significantly boosts computational efficiency and reduces the energy costs associated with data movement between processors and memory in traditional architectures. Our work represents the first physical demonstration of performing matrix multiplication on an ECRAM array, setting a new benchmark for in-memory computing technologies and their application in advanced AI systems.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Materials Science & Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2024

Author dc:creator

• Cui, Jinsong

Contributors dc:contributor

• Cao, Qing
• Zuo, Jian-min
• Ghose, Saugata
• Zhang, Yingjie

• Ecram
• Deep Learning
• Semiconductor
• Cmos
• Neuromorphics
• Training
• Nonvolatile Memory
• Programming

Statement dc:rights

• Copyright © 2024 by Jinsong Cui. All rights reserved.

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/127349

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F127349