Energy-efficient Resistive In-memory Computing Architectures

Embedded non-volatile memory (eNVM)-based in-memory computing (IMC) architectures have garnered significant interest due to their high memory density and non-volatility in realizing efficient implementations of deep neural networks (DNNs). Their high density enables on-chip storage of DNN models, thereby reducing the energy and latency costs associated with data movement. Additionally, their non-volatile nature supports efficient activity-driven duty-cycled operations. However, these benefits have not been realized in real-life eNVM-based IMC integrated chip (IC) prototypes, which significantly lag behind SRAM-based IMCs and digital accelerators in terms of energy efficiency and compute density. This lag is primarily due to the presence of large read-out circuits required to achieve high bank-level accuracy. Moreover, the fundamental energy-accuracy trade-offs of eNVM-based IMCs are not well understood, as most research focuses on achieving high network-level accuracy, which masks bank-level accuracy due to the error tolerance of DNNs and the use of noise-aware training. This dissertation aims to evaluate the intrinsic energy-accuracy trade-offs of eNVM-based IMCs and develop techniques to enhance bank-level accuracy. First, we introduce a comprehensive benchmarking methodology for IMCs that quantifies the significant lag in energy efficiency and compute density of eNVM-based IMCs compared to SRAM-based IMCs and digital accelerators. Second, to understand this lag, which arises from the low bank-level accuracy of resistive IMCs, we use the compute signal-to-noise-plus-distortion ratio (SNDR) to measure accuracy and identify its dependence on device, circuit, and architectural parameters. This is achieved by developing a chip-verified behavioral model, which reveals that the maximum achievable SNDR is limited by pre-analog-to-digital-converter (ADC) analog non-idealities. Additionally, we find that increasing the device-level conductance contrast improves the maximum achievable SNDR only up to a certain point, beyond which it saturates. Third, building on insights from the behavioral model, we propose two bank-level accuracy-boosting techniques at the circuit and algorithmic levels, demonstrating a compute SNDR improvement from 2.7 to 6dB in a 22nm MRAM-based IMC prototype. This boost is traded off to achieve a 5x reduction in energy per 1b-operation, with modest energy and area overhead. Furthermore, our work shows that the bank-level accuracy boost correlates well with network-level accuracy without resorting to noise-aware training. Lastly, we explore the security vulnerabilities of eNVM-based IMC architectures against model extraction attacks (MEAs). These attacks can reconstruct private training data from trained model parameters, leaking sensitive user information. While the presence of analog noise in eNVM-based IMC computation might suggest intrinsic robustness to MEAs, we demonstrate that this is not the case. Our results underscore the critical importance of investigating the security vulnerabilities of IMCs in general and eNVM-based IMCs in particular.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2024

Author dc:creator

• Roy, Saion Kumar

Contributors dc:contributor

• Shanbhag, Naresh
• Hanumolu, Pavan
• Ghose, Saugata
• Seo, Jae-sun

• Sram
• Envm
• Mram
• Compute Sndr
• Model Extraction Attacks
• Security Vulnerabilities
• In-memory Computing
• Resistive Imc
• Benchmarking

Statement dc:rights

• Copyright 2024 Saion Kumar Roy

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/125621

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F125621