Parallel and heterogeneous computing for static timing analysis

The increasing complexity in digital design has spurred demand for faster design closure. As a primary timing measurement tool frequently used in design stage and optimization stage, static timing analysis (STA) has become one of the major performance bottlenecks in digital design. In this thesis, we study a novel parallel programming model and heterogeneous computing algorithms to boost timing analysis. As multi-core systems have become common in modern electronics, how to fit timing analysis into the multi-threading and heterogeneous computing environment is a trending research topic. We explore this direction with a new task-based multi-threading framework and several heterogeneous computing algorithms. We demonstrate their superior efficiency over existing tools. Critical path generation is a major objective timing analysis. Optimization tools always need to report on critical paths under several path constraints. In Chapter 1, we propose a path generation algorithm which can fulfill all practical path constraints and outperforms an industrial timing analysis tool. We also highlight its potential for multi-threading by leveraging a unified framework to task dependency graph, called Taskflow. In Chapter 2, we point out the scalability limitation by parallelizing with a multi-core CPU system. So we are highly motivated to accelerate the process of path generation in Path-based Analysis (PBA) within a heterogeneous computing environment. Our GPU-accelerated algorithm promotes PBA to a new performance milestone. In Chapter 3, we introduce an algorithm that enables path constraints satisfaction on the GPU. Our algorithm maintains high computation throughput while exploring critical paths in the search space required by the path constraints. In Chapter 4, we further improve our GPU-accelerated PBA algorithm with fine-grained optimizations. We integrate these optimizations together as a unified framework, which achieves speed-up for 3–5 times. In Chapter 5, we propose a STA graph partitioning framework that overcomes the GPU memory bottleneck. We believe this partitioning framework can allow us to offload the STA workload of industrial designs to multiple GPUs for further acceleration. The last chapter concludes this thesis and highlights the main contributions. We also point to several directions for the future work.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2023

Author dc:creator

• Guo, Guannan

Contributors dc:contributor

• Wong, Martin D.F.
• Huang, Tsung-Wei
• Chen, Deming
• Patel, Sanjay

• Static Timing Analysis
• Parallel And Heterogeneous Computing

Statement dc:rights

• Copyright 2023 Guannan Guo

Language dc:language

en, eng

Handle dc:identifier

https://hdl.handle.net/2142/120199

OAI record oai:identifier

https://www.ideals.illinois.edu/oai-pmh?verb=GetRecord&metadataPrefix=etdms&identifier=oai%3Awww.ideals.illinois.edu%3A2142%2F120199