Back to results
University of Illinois at Urbana-Champaign
A study of worst-case integrated circuit optimization using iEDISON3.0
Abstract
dc:descriptionOpen Restriction set for Item 116502 on 2020-10-22T17:38:13Z with date null by madinag@illinois.edu.
Degree
thesis:*- Name thesis:degree_name
- M.S. (master's)
- Level thesis:degree_level
- Thesis
- Discipline thesis:degree_discipline
- Electrical Engineering
- Grantor
- University of Illinois at Urbana-Champaign
- Year dc:date
- 2020
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Bieker, John Joseph
- Contributors dc:contributor
-
- Kang, Sung-Mo
Subjects
dc:subject × 1Rights
- Language dc:language
- en
Identifiers
dc:identifier.*- Handle dc:identifier
- http://hdl.handle.net/2142/108870
- OAI identifier oai:identifier
- oai:www.ideals.illinois.edu:2142/108870