Boosting static timing analysis with programming and algorithmic approaches

The increasing complexity in digital design has spurred demand for faster design closure. As a primary timing measurement tool frequently used in design stage and optimization stage, static timing analysis has become one of the major performance bottlenecks in digital design. We study a novel parallel programming model and algorithm to boost timing analysis. As multi-core systems have become common in modern electronics, how to fit timing analysis into the multithreading environment is a trending research topic. We explore this direction with a new task-based multithreading framework and demonstrate its superior efficiency over existing tools. Critical path generation is a major objective timing analysis. Optimization tools always need to report on critical paths under several path constraints. We propose a general path search algorithm which can fulfill all practical path constraints and outperforms an industrial timing analysis tool. Combining the tasks proposed above, we aim to improve the efficiency of static timing analysis with both a new programming framework and new algorithm.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2020

Author dc:creator

• Guo, Guannan

Contributors dc:contributor

• Wong, Martin D.F.

• Static Timing Analysis
• Parallel Programming

Statement dc:rights

• Copyright 2020 Guannan Guo

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/108153

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/108153