Predictable inter-core communication for strictly partitioned real-time multi-core systems

The Federal Aviation Administration (FAA) in its recent CAST-32A certification guidance suggests that more than one core in a multi-core chip for safety-critical avionics applications can be used only if all the inter-core interference channels have been bounded and accounted for. Researchers have proposed frameworks to partition and regulate access to shared resources, such that multi-core processors can be deployed for safety-critical avionics applications. Strict partitioning of memory resources among cores, however, does not allow inter-core communication. In this paper, we propose a Communication Core Model(CCM) that implements the inter-core communication by bounding the amount of intercore interference in a partitioned multi-core system. A system level perspective of how to realize such CCM along with the implementation details is provided. A formula to derive WCET of the tasks using CCM is provided. We compare our CCM with Contention-based Communication (CBC) where no private banking is enforced for any core. The results of the analytical approach using San Diego Vision Benchmark Suite (SD-VBS) for two models indicate that the CCM shows an improvement of up to 65 percent when compared to the CBC. Moreover, our experimental results indicate that the measured WCET of the tasks of SD-VBS is within the bounds calculated using the proposed analysis.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Computer Science

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2019

Author dc:creator

• Wen, Jen-Yang

Contributors dc:contributor

• Sha, Lui

• Multi-core
• Inter-core communication
• hard real-time

Statement dc:rights

• Copyright 2019 Jen-Yang Wen

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/105237

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/105237