Reducing memory persistency overheads with transparent out-of-place updates

Recent advances in memory technology have led to the creation of high-performance, non-volatile alternatives to traditional DRAM, known as non-volatile memory (NVM). While this technology has provided immense opportunities to system designers, it has also presented new challenges since applications running on NVM systems require data persistence guarantees with respect to system crashes. To address this problem, many crash-consistency techniques, including logging and shadow paging, have been proposed. However, existing solutions can suffer from significant overheads on the critical path of execution or introduce extra write traffic to NVM, or even both. For instance, logging approaches introduce double writes for data and logs in the critical path of program execution, while shadow paging incurs significant write amplification and cache flushes to ensure durability. To provide persistence guarantees, this work proposes a transparent and efficient out-of-place update mechanism which provides atomic data durability without incurring a substantial number of additional writes or performance overheads. The key idea of the proposed approach is to write the updated data to a new location in NVM while keeping the old data unmodified until after the updated version becomes durable. To support out-of-place updates in NVM, this work introduces a lightweight and transparent persistence indirection layer, called PIL, along with minor changes to existing processor architectures which together enable efficient transaction execution in hardware. Experimental results with a variety of data structures and data-intensive applications show that PIL achieves low critical-path latency with small write amplification, which is close to that of a native system without persistence support. Compared with the state-of-the-art crash-consistency techniques, it improves application performance by up to 1.8× while reducing write amplification by up to 85.3%. PIL also demonstrates scalable data recovery capability on multi-core systems.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2019

Author dc:creator

• Coats, Chance Christopher

Contributors dc:contributor

• Huang, Jian

• Non-volatile Memory
• NVM
• Persistence
• Memory Persistence
• Crash-consistency

Statement dc:rights

• Copyright 2019 Chance Christopher Coats

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/105096

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/105096