An on-chip three-level boost converter for energy harvesting application

The first on-chip three-level boost converter with 0.28 mm2 die size is implemented using 65 nm CMOS technology. Leveraging the advantages of hybrid switched capacitor converters, the converter manages to provide a maximum output voltage of 4.5 V with the available 2.5 V devices in this technology. The issue of capacitor imbalance, which has always been one of the factors that hinder high-efficiency power converters, is resolved by the hybrid current mode controller proposed in this work. The hardware implementation demonstrates that the capacitor converges to its balance voltage within 270 μs. A new level shifter circuitry is established in this thesis to mitigate the effect of asymmetrical gate signals by the level shifter. This delay-equalized level shifter is able to produce a symmetric delay less than 1 ns, allowing high-frequency phase-shifted switching operation in a hybrid switched capacitor (SC) converter. Together with both output voltage regulation and capacitor balancing, the converter operates efficiently up to 45 MHz for wide input range from 0.5 V to 3.0 V. This converter achieves a peak efficiency of 97.5% and peak output current of 83 mA.

Name thesis:degree_name

M.S.

Level thesis:degree_level

Thesis

Discipline thesis:degree_discipline

Electrical & Computer Engr

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2018

Author dc:creator

• Ng, Pei Han

Contributors dc:contributor

• Pilawa-Podgurski, Robert

• three-level boost converter
• hybrid
• switched capacitor (SC)
• current mode control
• delay-equalized
• level shifter
• capacitor balancing

Statement dc:rights

• Copyright 2018 Pei Han Ng

Language dc:language

en

Handle dc:identifier

http://hdl.handle.net/2142/101831

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/101831