RO-Based TDC Design with Configurable Resolution and Power for SPAD-Based TCSPC LiDAR Applications

Single-photon avalanche diodes (SPAD) are used to measure time-of-flight (ToF) using CMOS time-to-digital Converters (TDCs) for compact, low-cost, and highly integrated three-dimensional (3D) sensing. The TDC specifications are critical determinants of the system's range, resolution, and accuracy. The optimization of the TDCs requires modeling that captures the target application's design specifications and parameters under different operating scenarios. Since single-photon detection is fundamentally a stochastic process, a fast and accurate analytical model is presented try accounting for the effects of limited TDC conversion rate (CR). The model is used to relate the number of required TDCs per SPAD array to the 3D imager performance accounting for environmental factors such as ambient light and distance. The model permits architectural exploration to determine the number of TDCs required for a given array size. Monte Carlo numerical simulations verify the accuracy of the proposed method. It also reveals that the most critical performance metrics of TDCs in time-correlated single-photon counting (TCSPC) applications are their CR, area, and power consumption. TDCs formed by ring oscillators (ROs) are arrayable, scalable, and low power, making them suitable for SPAD-based TCSPC 3D sensing systems. The jitter of RO-based TDCs is studied as a function of their full-scale-range resulting in an expression for the TDC total jitter. The analysis also identifies a peak-signal-to-noise ratio (SNR) design point. Increasing the TDC's full-scale-range beyond this point entails increased jitter and, thus, ultimately a declining SNR. Finally, this thesis presents a multi-channel RO-based TDC architecture whose power consumption scales with its configurable resolution for power-sensitive applications. A 75% power savings is achieved by sharing one RO among five TDCs relative to non-shared architectures. Furthermore, such an architecture improves uniformity between neighboring TDC channels by avoiding oscillator mismatches. Here, a 5-channel 12-bit TDC is fabricated in 65 nm CMOS with an area of 1920 m2 per channel. It demonstrates a CR up to 1 GHz in simulation (limited to 125 MHz in measurements due to the following serializer) with a resolution configurable from 24 to 133 ps. At a CR of 125 MHz, the TDC power consumption is 0.1 mW and 1 mW per channel at 133 ps and 24 ps resolution, respectively.

Department dc:contributor.department

Electrical and Computer Engineering

Year dc:date.issued

2022

Author dc:creator

• Arvani, Foad

Advisor dc:contributor.advisor

• Carusone, Tony

• Counter
• Ring oscillator
• Single-photon Avalanche Diode (SPAD)
• Time-Correlated Single-photon Counting (TCSPC)
• Time-of-Flight (ToF) LiDAR
• Time-to-digital converter (TDC)

Handle dc:identifier.uri

http://hdl.handle.net/1807/110841

OAI identifier oai:identifier

oai:utoronto.scholaris.ca:1807/110841