Reliable processing-in-memory

Processing-in-memory (PIM) architectures integrate compute units within memory, enhancing performance and efficiency but introducing significant reliability challenges. These challenges arise from the inherent conflict between localized data accesses, which minimize data movement, and the necessity for non-local accesses to manage error-checking and correcting (ECC) metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. I show that my mechanisms can minimize performance overhead while enhancing reliability.

Name thesis:degree_name

Doctor of Philosophy

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor

The University of Texas at Austin

Year dc:date.issued

2025

Author dc:creator

• Jung, Jeageun

Advisor dc:contributor.advisor

• Erez, Mattan

Committee members dc:contributor.committeemember

• Gerstlauer, Andreas
• Swartzlander, Earl
• Gurumurthi, Sudhanva
• Orshansky, Michael

• PIM
• Processing-in-memory
• Reliability
• ECC
• DRAM

Identifier URI

https://doi.org/10.26153/tsw/61036

OAI identifier oai:identifier

oai:repositories.lib.utexas.edu:2152/133707