{"id":{"repo_id":"texas","oai_identifier":"oai:repositories.lib.utexas.edu:2152/133707"},"canonical_url":"https://search.dev.ndltd.org/etd/texas/oai:repositories.lib.utexas.edu:2152/133707","repository":{"repo_id":"texas","name":"University of Texas","base_url":"https://repositories.lib.utexas.edu/server/oai/request"},"display":{"title":"Reliable processing-in-memory","abstract":"Processing-in-memory (PIM) architectures integrate compute units within memory, enhancing performance and efficiency but introducing significant reliability challenges. These challenges arise from the inherent conflict between localized data accesses, which minimize data movement, and the necessity for non-local accesses to manage error-checking and correcting (ECC) metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. I show that my mechanisms can minimize performance overhead while enhancing reliability.","abstract_html":"Processing-in-memory (PIM) architectures integrate compute units within memory, enhancing performance and efficiency but introducing significant reliability challenges. These challenges arise from the inherent conflict between localized data accesses, which minimize data movement, and the necessity for non-local accesses to manage error-checking and correcting (ECC) metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. I show that my mechanisms can minimize performance overhead while enhancing reliability.","abstract_has_math":false,"creators":["Jung, Jeageun"],"institution":"The University of Texas at Austin","degree_name":"Doctor of Philosophy","degree_level":null,"degree_discipline":"Electrical and Computer Engineering","degree_department":null,"school":null,"contributors":[],"advisors":["Erez, Mattan"],"committee_chairs":[],"committee_members":["Gerstlauer, Andreas","Swartzlander, Earl","Gurumurthi, Sudhanva","Orshansky, Michael"],"year":2025,"date_issued":"2025-05","date_published":"2025-05","updated_at":"2026-07-24T05:01:22Z","subjects":["PIM","Processing-in-memory","Reliability","ECC","DRAM"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://doi.org/10.26153/tsw/61036"],"render_values":[{"text":"https://doi.org/10.26153/tsw/61036","href":"https://doi.org/10.26153/tsw/61036","code":true}]}]},"links":{"outbound_url":"https://hdl.handle.net/2152/133707","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Erez, Mattan"]},{"key":"dc:contributor.committeemember","label":"Committee Member","values":["Gerstlauer, Andreas","Swartzlander, Earl","Gurumurthi, Sudhanva","Orshansky, Michael"]},{"key":"dc:creator","label":"Author","values":["Jung, Jeageun"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2025-07-23T20:31:07Z"]},{"key":"dc:date.issued","label":"Date","values":["2025-05"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical and Computer Engineering"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy"]},{"key":"thesis:institution_name","label":"Thesis Institution Name","values":["The University of Texas at Austin"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["PIM","Processing-in-memory","Reliability","ECC","DRAM"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/2152/133707","https://doi.org/10.26153/tsw/61036"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Processing-in-memory (PIM) architectures integrate compute units within memory, enhancing performance and efficiency but introducing significant reliability challenges. These challenges arise from the inherent conflict between localized data accesses, which minimize data movement, and the necessity for non-local accesses to manage error-checking and correcting (ECC) metadata. I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. 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I introduce a novel DRAM physical fault model based on empirical data and an ECC scheme specifically designed for PIM. I develop a predictive model based on a public dataset of DRAM errors which provides predictions based on a mapping to physical components in any DRAM, instead of relying on retrospective data that is only valid for already-deployed (older) DRAM technology. I also propose an ECC scheme that targets the read-dominant access patterns of near memory processing and addresses DRAM errors reported in DRAM error field studies. Furthermore, I explore reliable bank-level PIM architectures for irregular access patterns to support more applications. I demonstrate my approach in a simulated system that uses the physical fault model and a DDR5-PIM with several ECC schemes. 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