FPGA Based Matrix Multiplication Accelerator

The demand for fast matrix multiplication continues to increase due to recent advances in image processing, graphics processing, digital signal processing, and communication over the wireless network. Therefore, the development of a hardware-based matrix multiplication is essential, which is efficient and capable of performing a quick operation because the hardware-based multiplication in matrix multiplication requires a higher amount of processing power and time. In order to design such kind of hardware, the non-zero-digit count of a number must be kept to minimum, which minimizes the partial products that result when multiplying it by another number. This also shortens the time required to complete the multiplication process because it lowers the number of add operations. The Factor Canonical Signed Digit (FCSD) method can minimize the number of partial products created during multiplication and eliminate the need for a dedicated multiplier. This work proposes a hardware design on the Field Programmable Gate Array (FPGA), which accelerates the matrix dimensions from 2 × 2 to 32 × 32 with elements represented by 8, 16, and 32-bits utilizing the FCSD approach and pipeline structure. All design and simulation are performed using Xilinx Vivado ML edition 2023.2 tool which uses Artix 7 AC701 evaluation board for synthesis and implementation.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

Masters

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

Texas State University

Year dc:date.issued

2024

Author dc:creator

• Deb, Polash

Advisor dc:contributor.advisor

• Aslan, Semih

Committee members dc:contributor.committeemember

• Stern, Harold P.E.
• Valles, Damian

• matrix multiplication
• CSD
• FCSD
• FPGA

Language dc:language.iso

en

Handle dc:identifier.uri

https://hdl.handle.net/10877/20516

OAI identifier oai:identifier

oai:digital.library.txst.edu:10877/20516