Methodology for Standby Leakage Power Reduction in Nanometer-Scale CMOS Circuits

<p>In nanometer-scale CMOS technology, leakage power has become a major component of the total power dissipation due to the downscaling of threshold voltage and gate oxide thickness. The leakage power consumption has received even more attention by increasing demand for mobile devices. Since mobile devices spend a majority of their time in a standby mode, the leakage power savings in standby state is critical to extend battery lifetime. For this reason, low power has become a major factor in designing CMOS circuits.</p> <p>In this dissertation, we propose a novel transistor reordering methodology for leakage reduction. Unlike previous technique, the proposed method provides exact reordering rules for minimum leakage formation by considering all leakage components. Thus, this method formulates an optimized structure for leakage reduction even in complex CMOS logic gate, and can be used in combination with other leakage reduction techniques to achieve further improvement.</p> <p>We also propose a new standby leakage reduction methodology, leakage-aware body biasing, to overcome the shortcomings of a conventional Reverse Body Biasing (RBB) technique. The RBB technique has been used to reduce subthreshold leakage current. Therefore, this technique works well under subthreshold dominant region even though it has intrinsic structural drawbacks. However, such drawbacks cannot be overlooked anymore since gate leakage has become comparable to subthreshold leakage in nanometer-scale region. In addition, BTBT leakage also increases with technology scaling due to the higher doping concentration applied in each process technology. In these circumstances, the objective of leakage minimization is not a single leakage source but the overall leakage sources. The proposed leakage-aware body biasing technique, unlike conventional RBB technique, considers all major leakage sources to minimize the negative effects of existing body biasing approach. This can be achieved by intelligently applying body bias to appropriate CMOS network based on its status (on-/off-state) with the aid of a pin/transistor reordering technique.</p>

Name thesis:degree_name

Doctor of Philosophy (PhD)

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering and Computer Science

Year

2012

Author dc:creator

• Chun, Jae Woong

Contributors dc:contributor

• C. Y. Roger Chen

• Leakage currents
• Low power design
• Minimum leakage vector
• Stacking effect
• Substrate bias
• Technology scaling
• Electrical and Computer Engineering

Repository record dc:identifier

https://surface.syr.edu/eecs_etd/328

OAI identifier oai:identifier

oai:surface.syr.edu:eecs_etd-1332